With the continued emphasis on highly integrated electronic devices, there is an ongoing need for semiconductor devices that operate at higher speeds and lower power and have increased device density. To achieve these goals, it is necessary for devices to be formed with increased integration and for device components to be formed of lower-resistivity materials. However, as the patterns used to form device components become smaller and as the space between adjacent patterns also becomes smaller, there is a greater likelihood of leakage current propagating between neighboring patterns and components.
To illustrate this problem, in a common configuration for contemporary semiconductor devices, an interlayer contact formed of tungsten is formed in a first interlayer dielectric layer, an etch stop layer, for example silicon nitride, is formed on the first interlayer dielectric layer and a second interlayer dielectric layer is formed on the etch stop layer. A copper bit line pattern is formed in the second interlayer dielectric layer in contact with a top of the underlying interlayer contact. Adhesion between the etch stop layer with the underlying first interlayer dielectric layer is generally weak, and, as a result, when the copper bit line patterns are formed, copper diffusion can occur along the interface of the etch stop layer and the first interlayer dielectric layer. Even in a case where the etch stop layer is not used, copper diffusion can occur at the interface of the underlying first interlayer dielectric layer and the second interlayer dielectric layer.
With increased integration of semiconductor devices, neighboring bit line patterns are formed closer in proximity to each other, and this increases the likelihood of leakage current flowing between adjacent bit line patterns, especially through the region of copper diffusion along the interface of the etch stop layer and the first interlayer dielectric or along the interface of the first and second interlayer dielectric layers. In addition, with increased integration, misalignment of the bit lines relative to the underlying interlayer contact is more likely to occur, due to the relative reduced distance between them, and thus a second form of leakage current can occur between the underlying interlayer contact and a neighboring bit line.